1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to methods of improving single layer resist (SLR) patterning schemes.
2. Background Art
Conventional semiconductor fabrication uses single layer resist (SLR) patterning schemes for etching underlying layers. Typically, the SLR patterning scheme employs a patterned SLR layer positioned over an anti-reflective coating (ARC), which is opened to expose the underlying layer to be etched. As the semiconductor industry continues to drive toward reduced feature size, however, one of the biggest challenges for SLR patterning schemes is maintaining the resist pattern fidelity throughout the subsequent image transfer procedures, including etching through the ARC layer and the underlying layers. Inadequate resist thickness through the etch process results in degradation or sometimes total loss of the patterned images. In other words, conventional SLR patterning schemes do not present sufficient etch resistance. FIGS. 1-2 show an illustrative etching process in which a patterned SLR 100 is positioned over an ARC layer 102, which is positioned over an underlying layer 104. As an ARC open etch 110 (FIG. 2) proceeds, patterned SLR 100 becomes significantly thinner, which prevents continued use of patterned SLR 100.
One approach to mitigating this issue is to increase the SLR layer thickness and/or decrease the ARC thickness. However, the decision on the optimal operating SLR layer thickness is generally associated with the reflectivity swing curve (i.e., a sinusoidal variation of reflectivity as a function of resist thickness), and the increase in SLR layer thickness often results in process window reduction due to issues like resist line collapse or resist profile degradation. Reducing the operating thickness of each given ARC is also unfavorable due to concerns on the reflectivity control and sometimes on the coverage of topography. Other common manufacturing solutions for the SLR patterning scheme problem include implementing SLR patterning schemes with inorganic hard mask, bi-layer or tri-layer processes. Each of these solutions, however, requires changes to the integration scheme, adding process costs and increasing complexity.
Improving resist etch resistance has been employed, for example, as disclosed in U.S. Pat. No. 6,753,129, issued to Livesay et al. In this disclosure, a photoresist is modified by electron beam exposure. While this technique improves resist etch resistance, it does not address the difficulties presented by an ARC, which is not used in the particular resist scheme of that disclosure.
In view of the foregoing, there is a need in the art for a way to mitigate the etch burden of selective photoresists and therefore extend the application of the single layer resist (SLR) patterning scheme to beyond the current physical limit.